1. Field of the Invention The present invention relates to Class-D amplifier circuit which may be used, for example, as a power amplifier circuit of audio amplifier.
2. Description of the Related Art
FIG. 1 is a block diagram illustrating a conventional class-D amplifier circuit. As shown, the conventional class-D amplifier circuit includes pulse-width modulator 1, drive signal generator 2, output driver 3, and low-pass filter (LPF) 4.
The pulse-width modulator 1 converts an analog audio input (AIN) signal into binary pulse train (i.e., a pulse-width modulated PWM signal) having a duty ratio which is proportional to an amplitude of the AIN signal. The PWM signal (e.g., 1-MHz digital signal) can be obtained, for example, by utilizing a comparator to compare the AIN signal to a high-frequency saw-tooth wave signal.
The drive signal generator 2 converts the PWM signal into two drive signals, namely, a PGC drive signal and an NGC drive signal. As shown in FIG. 1, the PGC drive signal is applied to the gate of a PMOS transistor 3p of the output driver 3, and the NGC drive signal is applied to the gate of an NMOS transistor 3n of the output driver 3.
In operation, for example, the drive signal generator 2 outputs a PGC signal which turns ON the PMOS 3p when the logic level of pulse-width modulated PWM signal is “H” (high), and outputs an NGC signal which turns ON the NMOS 3n when the logic level of pulse-width modulated PWM signal is “L” (low). The drive signal generator 2 may be configured to avoid simultaneous driving both of the PMOS 3p and the NMOS 3n when the pulse-width modulated PWM signal is transitioning between logic levels.
As mentioned above, the output driver 3 includes the PMOS 3p and the NMOS 3n. The PMOS 3p and the NMOS 3n are connected in series between a positive voltage VSS and a negative voltage VDD, with an output of the output driver 3 being located at a connection node N.
In this conventional example, when the pulse-width modulated PWM signal is “H”, the PMOS 3p is ON and NMOS 3n is OFF, and the potential at node N is roughly equal to the positive voltage VDD. Conversely, when the pulse-width modulated PWM signal is “L”, the PMOS 3p is OFF and NMOS 3n is ON, and the potential at node N is roughly equal to the negative voltage VSS.
High-frequency components of the output of the output driver 3 are removed by the LPF 4 to obtain an amplified voice band analog output signal OUT. The output signal OUT is supplied to a load, such as speakers (not shown).
The PMOS 3p and the NMOS 3n of the output driver 3 function as switching elements, and the most significant signal power loss factor of the output driver 3 is PD loss (power dissipation loss) attributable to the on-resistance RON of the switch devices PMOS 3p and NMOS 3n. PD loss can be represented by the following equation:PD=IO2×RON=(PO/RL)×RONwhere IO is the magnitude of an output current, RL is the load resistance, RON is the on-resistance of the switch devices, and an PO is the output power.
Namely, PD loss is proportional to the output power PO and the on-resistance RON of the switch element. Therefore, any decrease in the on-resistance RON of the switch elements PMOS 3p and NMOS 3n will result in a decrease in the PD loss (assuming the output power PO remains the same).
However, as discussed below, there are significant constraints to be dealt with in attempting to decrease the on-resistance of the switch elements PMOS 3p and NMOS 3n. 
The on-resistance (output impedance) of a PMOS device or an NMOS device can be approximated in accordance with the following equation:RON=1/(K×(W/L)×(VGON−VT))where K is a coefficient by determined a manufacturing process, L and W are a gate width and a gate length of the NMOS or PMOS device, respectively, VGON is a gate voltage during an ON-state of the PMOS or NMOS device, and VT is a threshold voltage of the NMOS or PMOS device.
The variables VT, L and K are all constrained by manufacturing processes and/or limitations, and the variable VGON is constrained by the practical need to utilize a normal power supply voltage. Further, while it may be practical to increase the gate width W, the result would be an adverse increase in gate drive power.
That is, as the gate width W of the NMOS or PMOS device increases, the gate capacitance CG also increases. The power needed to drive the gate of the NMOS or PMOS device may be represented by the following equation:PG=CG×VGON2×FSW where CG is gate capacitance, VGON is a gate voltage during an ON-state of the PMOS or NMOS device, and FSW is a switching frequency.
Thus, an increase in gate capacitance will result in a proportional increase in power needed to drive the gates of the NMOS and PMOS devices, which in turn can reduce the power efficiency of the class-D amplifier.